In synchronous systems, devices in the system are clock clocked by an external clock signal and perform operations at predetermined times relative the rising and falling edges of the clock signal. For example, in a typical memory system, a memory controller applies commands to synchronous memory devices and data is transferred between the memory devices and the controller in synchronism with an external clock signal applied to the controller and memory devices. In the memory system, the memory controller must place write data being transferred to the memory devices on a data bus at the proper times relative to rising and falling edges of the external clock signal to ensure that the memory devices successfully capture the data. Similarly, the memory devices must place read data being transferred to the controller on the data bus at proper times relative to rising and falling edges of the clock signal to ensure the controller successfully captures the data.
FIG. 1 is a simplified block diagram of a conventional memory system 100 including a synchronous memory 102, such as a DDR SDRAM, coupled to a memory controller 104 through an address bus ADDR, data bus DATA, and control bus CONT. An external clock signal CLK is applied to the memory 102 and controller 104, and the transfer of data over the ADDR, DATA, and CONT busses occurs at proper times relative to edges of the CLK signal to ensure a receiving device successfully captures the data being transferred. The data bus DATA includes a data strobe signal DQS that the memory 102 applies on the data bus DATA along with a read data word DQ1–N, and the memory controller 104 uses the DQS signal to successfully capture the read data word. During write operations, the memory controller 104 applies the DQS signal on the data bus DATA along with a write data word DQ1-N, and the memory 102 uses the DQS signal to successfully capture the write data word. The memory controller 104 also supplies a data masking signal DM to the memory 102 over the data bus DATA to control the masking of write data being transferred to the memory.
In operation, the memory controller 104 applies a data transfer command to the memory 102 in the form of appropriate address and control signals on the ADDR and CONT busses, respectively. The memory latches the applied command in response to a rising edge of the CLK signal, and thereafter decodes and processes the latched command. In response to a read command, the memory 102 accesses the addressed data, places the data on the data bus DATA as one or more read data words DQ1–N, and strobes or drives the DQS signal. The memory controller 104 captures read data words DQ1–N in response to rising and falling edges of the DQS signal. During write operations, in addition to applying a write command to the memory 102, the memory controller 104 places write data words DQ1–N on the data bus DATA and drives the DQS signal. In response to the write command, the memory 102 captures write data words DQ1–N in response rising and falling edges of the DQS signal, and stores the write data words in locations corresponding to the supplied address. The memory 102 also masks the DM signal applied coincident with each write data word DQ1–N, and masks or does not transfer the captured write data word to the addressed location when the DM signal is activated.
To successfully capture the data words DQ1–N being transferred over the data bus DATA, the DQS signal must be synchronized with the data words. During read operations, the memory 102 places each read data word DQ1–N on the data bus DATA in synchronism with a rising or falling edge of the DQS signal. In modern memory devices, the speed of the data bus is increasing, meaning that the frequency of the DQS signal is greater and the duration for which data words placed on the data bus are valid is decreasing (i.e., shorter read and write cycle times). As a result, shifts between the DQS signal and the data words become more critical since a smaller shift may now result in spurious data being captured. This is true because a smaller shift in the DQS signal relative to the data words may result in the memory 102 or controller 104 capturing the data words when the words are no longer valid, as will be appreciated by those skilled in the art.
A width N of the data bus DQ is being increased in modern synchronous memory devices to transfer more data to and from the memory 102 each cycle of the CLK signal, where the width N of the data bus is defined as the number of signals or bits N in a data word DQ1–N. This increase in the width N of the data bus DATA can result in an undesirable skew or shift of the read data words DQ1–N relative to the DQS signal. Such a shift can occur as more data drivers (not shown in FIG. 1) in the memory 102 draw more current from a power supply (not shown) in driving more bits in each data word DQ1–N from a first logic state to the complementary logic state when a new data word is being placed on the data bus DATA. Such a shift is known as simultaneous switching outputs (SSO) pushout, as will be understood by those skilled in the art. For example, if a first read data word DQ1–N includes all 0's and the next read data word includes all 1's, each data driver draws current from the power supply in driving the corresponding bit from a voltage level corresponding to a logic 0 to a voltage level corresponding to a logic 1. The larger the width N of the data bus DATA, the more data drivers required and the more current demanded from the power supply in this situation, and the larger the voltage drop across each data line due to an increased inductance L of each data line, as will be discussed in more detail below.
As the width N increases, the cumulative current required by all data drivers can exceed a maximum current capable of being supplied by the power supply. In this situation, the data drivers receive less current than required to drive the corresponding bits from a voltage level corresponding to a first logic state to a voltage level corresponding to the complementary logic state according to specified timing characteristics of the memory 102. One such timing characteristic is an access time, which defines a timing window around the transition of the DQS signal in which transitions of the bits in the data words must occur in order to allow the memory controller 104 to successfully capture the data words in response to the DQS signal. The reduced current causes the data drivers to drive the corresponding bits to the complementary logic states more slowly and thereby undesirable shifts the data word DQ1–N relative to the DQS signal, possibly shifting the data word outside the specified access time for the memory 102. The shift between the transition of the DQS signal and each data word DQ1–N depends on the number of bits changing logic state and the logic state to which the bits are changing, as will be understood by those skilled in the art. In addition to a reduced current being supplied to the data drivers, physical constraints on the size of the power lines (not shown) that supply power to the data drivers can result in the power lines having an inductance that causes a relatively large voltage drop to develop across the power lines when the data drivers demand a maximum current over a short period of time (V=Ldi/dt). Such a voltage drop can also slow the rate at which the data drivers drive the corresponding bits to the required voltage levels and shift the data words outside the specified access time.
FIG. 2 is a signal timing diagram illustrating shifts in the read data words DQ1–N relative to the DQS signal as the number of bits transitioning from a first logic state to the complementary logic state varies. In FIG. 2, three situations are illustrated where a new data word D0–2 is being placed on the data bus DATA with the prior data word on the data bus in each instance designated PD0–2, respectively. In the first situation, no bits are transitioning or changing state from the PD0 word to the D0 word (PD0=D0), and the data drivers place the D0 word on the data bus DATA in synchronism with the DQS signal at a time T0 and within a specified access time TAC of the memory 102. In the second situation, one half the bits change from a first logic state to the complementary logic state between the data words PD1 and D1. The data drivers place the D1 word on the data bus DATA at a time T1 just after the transition of the DQS signal at the time T0, which is also within the specified access time TAC. Thus, the data drivers place the data word D1 on the data bus more slowly relative to the data word D0 due to more bits changing from a first logic state to the complementary logic state.
In the third situation shown in FIG. 2, all bits change state between the data words PD2 and D2, and the data word D2 is placed on the data bus DATA at a time T2 after the transition of the DQS signal at the time T0. In this situation, the data word D2 is placed on the data bus DATA outside the specified access time TAC of the memory 102 due to the slower operation of the data drivers resulting from all N bits in the data word changing state. If the width N of the data bus DATA is increased, the data words will be delayed even more relative to the transition of the DQS signal when all or a large number of bits change from a first logic state to the complementary logic state, assuming the same power is supplied to the data drivers. Additional power could be supplied to the data drivers to eliminate these undesirable shifts, but it is not always practicable or cost effective to increase the power, as will be appreciated by those skilled in the art. The concepts described above have been discussed with reference to read operations because timing budgets for read cycles are typically tighter (less margin) than for write cycles and thus timing shifts are more critical, but the concepts are equally applicable to write cycles.
An approach that has been utilized in microprocessors, such as the Intel® Pentium® 4, is to include additional pins in the data bus for transferring one or more data bus inversion signals DBI generated by the processor. Each data bus inversion signal is associated with a group of bits, such as a byte, of data on the data bus. In operation, the processor determines whether more than half the bits in each byte would change logic state from a current byte on the data bus to a next byte to be placed on the data bus. If more than one half the bits in the byte would change logic state, the processor inverts the data bits in the next byte and activates the DBI signal associated with the byte. A receiving device, such as a memory controller, thereafter receives the next byte and the active DBI signal, and inverts the data in the next byte in response to the active DBI signal, thus returning the inverted data to its actual values. This approach requires the inclusion of additional pins on the processor and receiving devices, which increases the cost of the processor and receiving devices due to the increased number of pins, as will be appreciated by those skilled in the art. Moreover, as the width of the data bus increases, more DBI signals and associated pins are required, which consumes even more pins on the processor and receiving devices.
There is a need for a system and method for providing data words in synchronism with a clock signal in integrated circuits having wide data busses independent of the number of bits the data words changing from a first logic state to a complementary logic state.